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My projects reflect a profound interest and skill in digital design across various domains. Proficient in HDLs such as Verilog and adept with EDA tools, I engineer innovative solutions for advanced applications. My portfolio includes work on processors, accelerators, and cryptographic engines, each rigorously tested and simulated to ensure robustness and reliability. My approach integrates application engineering principles, demonstrating a commitment to excellence in every project.
A scalable and pipelined accelerator architecture for large-scale deep learning networks using FPGAs as the hardware prototype.
Implemented a high-performance AES-128 encryption engine using Verilog, subsequently simulating it on Modelsim.
Designed and implemented a high-performance matrix multiplication unit, optimized for efficient computation and resource utilization.
Spearheaded a team to design a 10-port router for NoC on an FPGA. The project was awarded by IISc, India.
Designed and implemented a single-cycle processor based on RISC-V architecture, utilizing open-source EDA toolchain.
Motivated and ambitious young professional, armed with hands-on experience in diverse projects spanning FPGA and ASIC architecture. With a solid grasp of AI hardware design principles, I'm driven by a fervent passion for the convergence of AI and computer architecture. Continually exploring the dynamic interplay between cutting-edge technologies, my aim is to catalyze innovation and elevate performance standards in the evolving landscape of future computing.
Cameron
One make creepeth man bearing their one firmament won't fowl meat over sea
Cameron
One make creepeth man bearing their one firmament won't fowl meat over sea
Cameron
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